1. Field of the Invention
The present invention relates to high density memory devices based on programmable resistive memory materials, including phase change materials like chalcogenides and others, and to methods for manufacturing such devices.
2. Description of Related Art
Phase change based memory materials are widely used in read-write optical disks. These materials have at least two solid phases, including for example a generally amorphous solid phase and a generally crystalline solid phase. Laser pulses are used in read-write optical disks to switch between phases and to read the optical properties of the material after the phase change.
Phase change based memory materials, like chalcogenide based materials and similar materials, also can be caused to change phase by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher resistivity than the generally crystalline state, which can be readily sensed to indicate data. Thus, phase change materials can be characterized as a type of programmable resistive memory material. These properties have generated interest in using phase change material and other programmable resistive memory material to form nonvolatile memory circuits, which can be read and written with random access.
The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change structure to stabilize in the amorphous state. It is desirable to minimize the magnitude of the reset current used to cause the transition of the phase change material from a crystalline state to an amorphous state. The memory cells using phase change material include an “active region” in the bulk of the phase change material of the cell in which the actual phase transitions are located. Techniques are applied to make the active region small, so that the amount of current needed to induce the phase change is reduced. Also, techniques are used to thermally isolate the active region in the phase change cell so that the resistive heating needed to induce the phase change is confined to the active region.
The magnitude of the reset current needed for reset can also be reduced by reducing the size of the phase change material element in the cell and/or the contact area between electrodes and the phase change material, such that higher current densities are achieved with small absolute current values through the phase change material element.
One direction of development has been toward forming small pores in an integrated circuit structure, and using small quantities of programmable resistive material to fill the small pores. Patents illustrating development toward small pores include: Ovshinsky, “Multibit Single Cell Memory Element Having Tapered Contact,” U.S. Pat. No. 5,687,112, issued Nov. 11, 1997; Zahorik et al., “Method of Making Chalogenide [sic] Memory Device,” U.S. Pat. No. 5,789,277, issued Aug. 4, 1998; Doan et al., “Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same,” U.S. Pat. No. 6,150,253, issued Nov. 21, 2000.
Another technology developed by the assignee of the present application is referred to as a phase change bridge cell, in which a very small patch of memory material is formed as a bridge across a thin film insulating member located between electrodes. The phase change bridge is easily integrated with logic and other types of circuitry on integrated circuits. See, U.S. application Ser. No. 11/155,067, filed 17 Jun. 2005, entitled “Thin Film Fuse Phase Change RAM and Manufacturing Method,” by Lung et al., incorporated by reference as if fully set forth herein, which application was owned at the time of invention and is currently owned by the same assignee.
Yet another approach to controlling the size of the active area in a phase change cell is to devise very small electrodes for delivering current to a body of phase change material. This small electrode structure induces phase change in the phase change material in a small area like the head of a mushroom, at the location of the contact. See, U.S. Pat. No. 6,429,064, issued Aug. 6, 2002, to Wicker, “Reduced Contact Areas of Sidewall Conductor;” U.S. Pat. No. 6,462,353, issued Oct. 8, 2002, to Gilgen, “Method for Fabricating a Small Area of Contact Between Electrodes;” U.S. Pat. No. 6,501,111, issued Dec. 31, 2002, to Lowrey, “Three-Dimensional (3D) Programmable Device;” U.S. Pat. No. 6,563,156, issued Jul. 1, 2003, to Harshfield, “Memory Elements and Methods for Making Same.”
One approach to the heat flow problem is seen in U.S. Pat. No. 6,815,704, entitled “Self Aligned Air-Gap Thermal Insulation for Nano-scale Insulated Chalcogenide Electronics (NICE) RAM”, in which an attempt is made to isolate the memory cell using gaps or voids on the sides of the phase change material. It has also been proposed to use thermally insulating materials to improve the confinement of heat to the active region.
Also, approaches to improving thermal isolation include forming the phase change element in a way that tends to isolate the active region from the electrodes, as shown for example in U.S. patent application Ser. No. 11/348,848, filed 7 Feb. 2006, entitled “I-Shaped Phase Change Memory Cell” by Chen et al., incorporated by reference as if fully set forth herein, which application was owned at the time of invention and is currently owned by the same assignee.
FIG. 1 illustrates a cross-sectional view of a portion of a prior art memory cell 100 including a memory member 110 comprising memory material having an active region 120 adjacent to a first interface structure 130. The memory member 110 makes electrical and thermal contact with the first interface structure 130, and also makes electrical and thermal contact with the second interface structure 140. The memory member 110 is surrounded by a dielectric 165 that acts to provide some thermal isolation to the memory member 110.
First interface structure 130 comprises a first conductive member 132 and a contact area 134 where the material of the first conductive member 132 contacts the memory material of the memory member 110. The first interface structure 130 is also electrically and thermally coupled to access circuitry (not shown) including an isolation device such as a transistor or a diode. The first interface structure 130 has a thermal impedance between the memory member 110 and the access circuitry.
Second interface structure 140 comprises a second conductive member 142 and a contact area 144 where the material of the second conductive member 142 contacts the memory material of the memory member 110. The second interface structure 140 is also electrically and thermally coupled to a bit line structure (not shown) including a bit line. The second interface structure 140 has a thermal impedance between the memory member 110 and the bit line structure.
In operation, bias circuitry (See, for example, bias circuitry voltage and current sources 1255 of FIG. 12) applying voltages to the isolation device and the bit line can induce current to flow from the first interface structure 130 to the second interface structure 140, or vice-versa, via the memory member 110. As current passes between the first and second interface structures 130, 140 and through the memory member 110, a portion of memory member 110 called the active region 120 heats up more quickly than the remainder of the memory member 110.
During reset the memory cell 100 is subject to a reset pulse having a pulse length of time, the reset pulse applied by the bias circuitry to transform the active region 120 of the memory member 110 to an amorphous phase. This reset pulse is a relatively high energy pulse, sufficient to raise the temperature of at least the active region 120 above the transition (crystallization) temperature Tx of the memory material and also above the melting temperature Tm of the memory material, thus placing at least the active region 120 in a liquid state. The reset pulse is then terminated, resulting in a relatively quick quenching time as the active region 120 quickly cools from melting temperature Tm to below transition temperature Tx such that the active region 120 stabilizes in an amorphous phase.
In FIG. 1 the active region 120 of the memory member 110 occurs adjacent to the first interface structure 130 because of a significant difference in the thermal impedances of the first and second interface structures 130, 140. A significant thermal impedance difference can cause, for example, heat transfer from the memory member 110 through the first interface structure 130 during quenching that is much greater than heat transfer from the memory member 1100 through the second interface structure 140. This can result in the portion of the memory member 110 nearest the first interface structure 130 undergoing cooling at a faster rate than the rest of the memory member 110, such that the active region 120 is adjacent the first interface structure 130.
Since the phase change of the active region 120 occurs as a result of heating and because the interfaces between the memory element 110 and the first and second interface structures 130, 140 are generally weak points, an interface adjacent to the active region 120 will undergo high temperatures that can increase the risk of failure of the interface. Therefore, issues can arise with the reliability of the memory cell 100 if the active region 120 is adjacent to an interface structure 130, 140.
Also, due to the high thermal conductivity of the interface structures 130, 140, if the active region 120 is adjacent to an interface structure 130, 140 a significant amount of heat will be drawn away from the active region 120, resulting in the need for a larger amount of power to induce the desired phase change in the active region 120. However, if the active region 120 is spaced away from the first and second interface structures 130, 140, the remaining portions of the memory element 110 can provide some thermal isolation to the active region 120 and thus reduce the amount of power needed to induce a phase change.
It is desirable therefore to provide a memory cell structure having an active region spaced away from the first and second interface structures to improve reliability and a reduce the amount of power needed for reset, as well as methods for manufacturing such devices.